Metal-oxide-semiconductor field effect transistors (MOSFETs) are known in the art. FIG. 1 shows a cross-section of a typical P-channel MOSFET device 10 which includes a lightly doped N- type substrate 11. Two highly doped P+ regions 12 and 14 are diffused or implanted into the substrate 11 to form a source and drain, respectively, as is known in the art. The P+ region 12 serves as a source through which majority carriers ("holes" in the case of a P-channel device or alternatively, electrons in the case of an N-channel device) enter the MOSFET device 10. The P+ region 14 serves as a drain through which the majority carriers, i.e., holes, exit the MOSFET device 10. A voltage bias V.sub.g, which is applied at the gate 16 of the MOSFET device 10, controls the amount of current flow of the majority carriers through the MOSFET device 10 between the source 12 and the drain 14. More specifically, the gate 16 in conjunction with a dielectric oxide layer 18 and the substrate 11 form a parallel plate capacitor, such that, by applying an appropriate gate voltage V.sub.g to the gate 16, an induced charge is created within a channel region of the substrate 11 located between the source 12 and drain 14 of the MOSFET device 10. As the gate voltage V.sub.g increases, so does the magnitude of the induced charge. As a result, the conductivity of the substrate 11 between the source 12 and drain 14 increases, and current is permitted to flow through the induced channel when a proper drain voltage is presented as is known.
When utilizing a P-channel MOSFET device, both the source 12 and substrate 11 typically are connected to the source voltage V.sub.s. The drain 14 is connected to the drain voltage V.sub.d which is at a lower potential than the source voltage V.sub.s. Thus, when the gate voltage V.sub.g is negative in relation to the source voltage V.sub.s, a positive charge is induced within the substrate 11 adjacent the dielectric layer 18. As is explained above, the induced positive charge creates a channel between the source 12 and drain 14 through which the majority carriers are permitted to travel, therefore resulting in current flow within the device 10.
An N-channel device is analogous to its P-channel counterpart described above. The N-channel device comprises a lightly doped P- type substrate into which two highly doped N+ type regions are diffused or implanted to form the source and drain. In the case of an N-channel device, an appropriate applied gate voltage V.sub.g will cause a negative induced charge to form between the N+ type source and drain. This negative induced charge permits the majority carriers, i.e., the electrons, to travel between the source and drain. Like the P-channel device, the substrate of the N-channel MOSFET device is typically connected along with the source region to the source voltage V.sub.s. The drain voltage V.sub.d, on the other hand, is at a higher potential than the source voltage V.sub.s. As a result, when a gate voltage V.sub.g is applied which is positive with respect to the source voltage V.sub.s, current is permitted to flow through the N-channel device.
Therefore, a MOSFET device, whether a P-channel or N-channel type, is commonly referred to as being turned "on" when the appropriate drain and gate biases V.sub.g and V.sub.d are present such that current is permitted to travel between source 12 and drain 14. When the appropriate gate and drain bias voltages are not present, the device is commonly referred to as being "off", due primarily to the very large impedance presented by the substrate 11 between the source 12 and drain 14.
As is described in detail in commonly assigned U.S. Pat. No. 4,490,629 entitled "High Voltage Circuits in Low Voltage CMOS Process", when the MOSFET device 10 is off and the drain 14 is connected through an external load device (not shown) to ground, a depletion region 20 in which the free majority charge carriers are depleted forms in the substrate 11 around the drain 14 as is shown in FIG. 1. Electrons are forced away from the drain 14 due to its relatively low voltage with respect to the substrate 11, which, as was previously described, is connected to a relative positive voltage V.sub.s in the case of a P-channel device. As the voltage difference between the drain 14 and the substrate 11 increases, the width of the depletion region increases, as is known in the art. However, as is shown in FIG. 1, the gate 16 of the P-channel device causes electrons to be attracted near the gate-substrate-drain interface. The influence of the gate voltage V.sub.g tends to force the electric fields to taper in near the edge of the drain at the gate interface. As is known in the art, this pinching or narrowing of the depletion region near the gate causes a reduction in the width of the depletion region to a width d.
Thus, for an increasing voltage differential between the drain 14 and the substrate 11, the effect of the gate voltage V.sub.g at the gate-drain interface results in a decreased depletion width d in which the electric field between the drain 14 and the substrate 11 increases in the area close to the surface. This forms the weakness for conventional MOSFET devices in high voltage applications. When the electric field between the drain 14 and the substrate 11 becomes sufficiently high, due to a high drain voltage V.sub.d for example, the PN junction formed between drain 14 and the substrate 11 breaks down under reverse-bias and current flows from the substrate 11 to the drain 14 near the gate interface. This phenomenon is hereinafter referred to as drain to bulk reverse-bias breakdown.
A more detailed description of the reverse-bias breakdown phenomenon is provided in the '629 patent.
The entire disclosure of U.S. Pat. No. 4,490,629 is hereby incorporated by reference.
For the reasons explained above, the reverse-bias breakdown voltage of a P-channel or N-channel MOSFET device 10 is an important parameter to consider when designing high voltage switching circuitry using CMOS technology. For example, FIG. 2 shows a conventional CMOS inverter 25 which provides an output voltage V.sub.out which is equal to either the voltage indicated as V.sub.dd or the voltage indicated as V.sub.ss, depending on the applied input voltage V.sub.in. As is shown in FIG. 2, input voltage V.sub.in is applied to the respective gates of devices M1 and M2. When the input voltage V.sub.in is a logic 1 (typically 5 volts), the P-channel device designated M1 turns off while the N-channel device designated M2 turns on. Therefore, the MOSFET device M1 exhibits a very high impedance, whereas, the device M2 exhibits a very low impedance, thus allowing current to flow only through the device M2. As a result, the output voltage V.sub.out is pulled down to what is sometimes referred to as the V.sub.ss rail, and the output V.sub.out therefore assumes the value of V.sub.ss. In the alternative, when the input voltage V.sub.in is a logic 0 (typically 0 volts), device M1 turns on and device M2 turns off, thereby causing the output voltage V.sub.out to be pulled up to the value of voltage V.sub.dd.
Regardless of whether the output voltage V.sub.out is equal to voltage level V.sub.dd or V.sub.ss at a particular moment in time, the MOSFET device in inverter 25 which happens to be off at that moment is subjected to a reverse bias voltage of approximately V.sub.dd, where V.sub.ss is considered to be digital ground. In the event voltage V.sub.dd is a substantially high voltage, the reverse bias voltage which will be imposed across the particular MOSFET device could result in a reverse bias breakdown of the device in the manner described above.
The '629 patent describes a CMOS high voltage push-pull output buffer which is designed to prevent high voltages from being applied across a given MOSFET device so as to avoid the occurrence of bulk to drain reverse-bias breakdown. The '629 patent described an output buffer in which a number of P-channel and N-channel devices are connected in source-to-drain series such that the voltage which is to be switched by the output buffer becomes evenly distributed across each series connected device, thus avoiding a large voltage being applied across a given device and resultantly increasing the switching capability of the overall circuit.
Referring now to FIG. 3, shown is a high voltage output buffer in accordance with the teachings of the '629 patent. In FIG. 3, P-channel devices designated M3 and M4 are connected in source-to-drain series with the similarly connected N-channel devices designated M5 and M6, forming a high voltage output buffer 30. As described in the '629 patent, gate voltages for the P-channel and N-channel devices are selected such that the relatively high supply voltage V.sub.vf substantially equally divides across the series connected P-channel devices in the event the P-channel devices are off and the N-channel devices are on. Alternatively, the high supply voltage V.sub.vf substantially equally divides across the series connected N-channel devices when the N-channel transistors are off and the P-channel devices on. In this manner, large reverse bias voltages across the MOSFET devices tend to be avoided.
As an example, when a logic 1 signal is applied to the control inputs designated CTRL1 and CTRL2, devices M5 and M6 are turned on while devices M3 and M4 are turned off, resulting in output voltage V.sub.out =V.sub.ss. As is taught in the '629 patent, with a bias voltage (from an appropriate source) of V.sub.bias =0.5 V.sub.vf applied to the gate of device M4, the source of device M4 will tend to remain at a voltage of approximately 0.5 V.sub.vf +V.sub.t, wherein V.sub.t is the threshold voltage of the MOSFET device. Meanwhile, the voltage at the source of device M3 will tend to remain at the value of supply voltage V.sub.vf as is shown in FIG. 3. As a result, the supply voltage V.sub.vf becomes substantially equally divided across each respective source to drain of the P-channel devices M3 and M4. More specifically, the voltage across each of the MOSFET devices which remain off is equal to one-half V.sub.vf.
Alternatively, in the case where a logic 0 control input signal is applied to control lines CTRL1 and CTRL2, devices M3 and M4 turn on and devices M5 and M6 turn off, thereby causing the output voltage V.sub.out to switch or be pulled up to the level of supply voltage V.sub.vf. The voltage at the drain of device M5 becomes that of the output voltage V.sub.out, or approximately the supply V.sub.vf. The voltage at the source of M5 remains at a value of approximately 0.5 V.sub.vf -V.sub.t, which corresponds to the source to drain voltage across device M6. In this case, therefore, the supply voltage designated V.sub.vf will be substantially equally divided across devices M5 and M6. As in the above case, the magnitude of the voltage across a given MOSFET device is limited to that of 0.5 V.sub.vf.
According to the explanatory embodiment shown in FIG. 3, where two P-channel and two N-channel devices are connected in series, a single bias voltage applied to the gates of M3 and M4 is sufficient to enable the supply voltage V.sub.vf to be substantially equally divided across the P-channel devices M3 and M4 when they are off, and alternatively, across the N-channel devices M5 and M6 in the event they are off. As is described in the '629 patent, the appropriate bias voltage V.sub.bias for the embodiment shown in FIG. 3 is V.sub.bias =0.5 V.sub.vf. This bias voltage is applied to the gates of both the P-channel device M4 and the N-channel device M5. Because an identical bias voltage ordinarily is applied to devices M4 and M5, in order that the supply voltage V.sub.vf will substantially equally divided across either the P or N-channel devices, M4 and M5 are referred to herein as forming a corresponding P-channel and N-channel pair.
More generally, a P-channel device and an N-channel device in the series-connected stack are referred to herein as forming a corresponding pair when an approximately equal bias voltage is applied to the respective gate in each of the devices in the pair in order that the output voltage V.sub.out becomes substantially equally divided across either the series-connected P-channel device or the N-channel device in the output buffer. The embodiment shown in FIG. 3 includes the corresponding pair of devices M4 and M5.
In an output buffer such as that shown in FIG. 3 of the drawings of the '629 patent, the output buffer may include three P-channel devices and three N-channel devices connected in series. In such an embodiment having three of each type of devices connected in series, two separate corresponding pairs are formed, each including a single P-channel and N-channel device. A bias voltage of 1/3 V.sub.vf is applied to the gates of a first P-channel device and a first N-channel device which make up a first corresponding pair. A bias voltage of 2/3 V.sub.vf is applied to the gates of a second P-channel device and a second N-channel device in the series connection which in turn make up a second corresponding pair. In the teachings of the '629 patent, a single bias line is utilized to provide the voltage to each gate in the corresponding pair.
While the exemplary prior art output buffer 30 shown in FIG. 3 utilizes two P-channel and two N-channel devices connected in series, other prior art embodiments included additional series-connected MOSFET devices so that the voltage across a given individual device was further reduced. As is taught in the '629 patent, in the event additional devices were connected in series, appropriate bias voltages which were typically approximately equal to integer fractions of V.sub.vf, were applied in a similar fashion to that described above to the gates of the additional corresponding pairs of P-channel and N-channel devices. The exact number and values of the addition bias voltages depended on the number of MOSFET devices which were connected in series in the output buffer 30. Therefore, while the background of the invention as well as the invention itself is described herein as involving primarily a high voltage output buffer having only two P-channel and two N-channel devices connected in series, it will be appreciated that such a configuration is intended to be merely exemplary. The various aspects of the present invention equally apply to high voltage output buffers having additional series connected devices with related bias voltages. As a result, the scope of the present invention is not intended to be limited to that of the exemplary embodiment.
As is evident in the above example, the '629 patent describes a push-pull output buffer 30 capable of switching high voltages using standard CMOS technology and/or processes. Complex fabrication processes for increasing the bulk to drain reverse bias breakdown voltage of the individual MOSFET devices are not required. The buffer 30 employs a plurality of P and N-channel devices connected in series in addition to appropriate gate biasing in order to distribute evenly the voltage across each device so that reverse bias breakdown voltage of each device may be avoided, even in the presence of high voltages.
There have been, however, a number of drawbacks associated with high-voltage output buffers of the type described in the '629 patent. For example, the voltages at the nodes between the series connected devices have been found to drift upon a switching of the output voltage V.sub.out. More specifically, a drift voltage node has been observed, for example, at a location indicated as node N1 of the output buffer 30, as is shown in FIG. 3. As is explained in detail below, such voltage drift at node N1 can stress the gate at the drain end of device M3. Under high voltage conditions, this stress can eventually lead to the failure of device M3 as well as the entire circuit 30. As an example, such stress related problems have often been found to arise in those applications in which the supply voltage V.sub.vf is greater than 30 volts.
Another problem which has been associated with prior high-voltage output buffers has been their inability to source sufficient current under low V.sub.vf conditions, for example, V.sub.vf .ltoreq.8 volts. In the exemplary output buffer shown in FIG. 3, the sourcing ability of each MOSFET device is proportional to its gate bias, or V.sub.gs -V.sub.t, where V.sub.gs is the gate to source voltage of the device and V.sub.t is its threshold voltage. Because the gate to source voltage V.sub.gs of each device is dependent on the value of the supply voltage V.sub.vf, the sourcing ability of these devices has been found to suffer under low V.sub.vf conditions. In the past, the above problem has been dealt with by increasing the size of each MOSFET device, thus increasing the channel width of each device so that a greater number of majority charge carriers are enabled to travel under low supply voltage V.sub.vf conditions. However, this increase in the size of each MOSFET device resulted, unfortunately, in both the inefficient use of the substrate 11 and in the increased cost of the output buffer.
Related to the inability of output buffers in the past to source sufficient current under low V.sub.vf voltage conditions was their restricted switching speed. More specifically, because the gate voltage typically applied was insufficient to turn the respective device fully "on", each device represented a relatively large impedance even in the "on" condition. This large impedance hindered the switching response time of the output buffer, as will be appreciated by one of ordinary skill in the art.
Yet another problem associated with such prior high-voltage output buffers has been the problem of noise on one or more of the bias lines. Oftentimes, multiple high-voltage output buffers 30 were driven by the same bias lines, these bias lines providing the appropriate bias voltages to similar corresponding pairs of P and N-channel MOSFETS. However, when the output voltage V.sub.out would be switched, for example, in a single output buffer with respect to the other output buffers 30 sharing the same bias line, the parasitic coupling occurring in the MOSFET devices in the switching buffer 30 tended to cause the voltage on the individual bias line or lines to be pulled up or down. As a result, it is evident that the effect of other output buffers 30 switching would be seen as noise on the bias line for a given high voltage output buffer 30.
Thus, there remains a strong need in the art for a method and apparatus for providing a highly stable high-voltage output buffer using conventional CMOS technology. More specifically, there remains a strong need for a method and apparatus for reducing or eliminating the problems caused by drift voltage nodes in a high-voltage output buffer without requiring elaborate processing of the CMOS device.
Furthermore, there is a need for a high-voltage output buffer which is capable of sourcing the necessary current under low V.sub.vf voltage conditions, without having to increase the size of the output device. In addition, there remains a strong need for a high-voltage output buffer capable of operating at a high switching speed. Even more, there remains a strong need for a high-voltage output buffer whose performance at low voltages is comparable to its performance at high voltages.
In addition, there remains a strong need for a high-voltage output buffer which may share one or more common bias lines with other of such output buffers while reducing the noise occurring along the shared bias lines.